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Abstract:

In this work a co-design flow for processor centric embedded systems with hardware acceleration using FPGAs is proposed. This flow helps to reduce design effort by raising abstraction level while not imposing the need for engineers to learn new languages and tools. The whole system is designed using well established high level modeling techniques, languages and tools from the software domain. That is, an OOP design approach expressed in UML and implemented in C++. Software coding effort is reduced since the C++ implementation not only provides a golden reference model, but may also be used as part of the final embedded software. Hardware coding effort is also reduced. The modular OOP design facilitates the engineer to find the exact methods that need to be accelerated by hardware using profiling tools, preventing useless translations to hardware. Moreover, the two-process structured VHDL design method used for hardware implementation has proven to reduce man-years, code lines and bugs in many major developments. A real-time image processing application for multiple robot localization is presented as a case study. The overall time improvement from the original software solution to the final hardware accelerated solution is 9.7x, with only 4% increase in area (143 extra slices). The embedded solution achieved following the proposed methodology runs 17% faster than in a standard PC, and it is a much smaller, cheaper and less power-consuming solution. © 2012 IEEE.

Registro:

Documento: Conferencia
Título:A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA
Autor:Pedre, S.; Krajník, T.; Todorovich, E.; Borensztejn, P.
Ciudad:Bento Goncalves
Filiación:Departamento de Computatión, Facultad de Ciencias Exactas Y Naturales, Universidad de Buenos Aires, Argentina
Department of Cybernetics, Faculty of Electrical Engineering, Czech Technical University in Prague, Czech Republic
Facultad de Ciencias Exactas, Universidad Nacional del Centro de la Provincia de Buenos Aires, Argentina
Palabras clave:Abstraction level; Co-design flow; Co-design methodology; Code line; Design approaches; Design effort; Design method; Exact methods; Hardware acceleration; Hardware implementations; Hardware-accelerated; High-level modeling; Multiple robot; Profiling tools; Real-time image processing; Reference models; Software coding; Software domains; Software solution; Design; Embedded software; Embedded systems; Engineers; Image processing; Robot applications; Hardware
Año:2012
DOI: http://dx.doi.org/10.1109/SPL.2012.6211770
Título revista:8th Southern Programmable Logic Conference, SPL 2012
Título revista abreviado:SPL - South. Program. Logic Conf.
Registro:https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_97814673_v_n_p_Pedre

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Citas:

---------- APA ----------
Pedre, S., Krajník, T., Todorovich, E. & Borensztejn, P. (2012) . A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA. 8th Southern Programmable Logic Conference, SPL 2012.
http://dx.doi.org/10.1109/SPL.2012.6211770
---------- CHICAGO ----------
Pedre, S., Krajník, T., Todorovich, E., Borensztejn, P. "A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA" . 8th Southern Programmable Logic Conference, SPL 2012 (2012).
http://dx.doi.org/10.1109/SPL.2012.6211770
---------- MLA ----------
Pedre, S., Krajník, T., Todorovich, E., Borensztejn, P. "A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA" . 8th Southern Programmable Logic Conference, SPL 2012, 2012.
http://dx.doi.org/10.1109/SPL.2012.6211770
---------- VANCOUVER ----------
Pedre, S., Krajník, T., Todorovich, E., Borensztejn, P. A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA. SPL - South. Program. Logic Conf. 2012.
http://dx.doi.org/10.1109/SPL.2012.6211770