Navegar

Colección

Datos Estadísticas

Conferencia

Asteasuain, F.; Braberman, V. "Specification patterns can be formal and still easy" (2010) 22nd International Conference on Software Engineering and Knowledge Engineering, SEKE 2010:430-436
Estamos trabajando para incorporar este artículo al repositorio

Abstract:

Property specification is still one of the most challenging tasks for transference of software verification technology like model checking. The use of patterns has been proposed in order to hide the complicated handling of formal languages from the developer. However, this goal is not entirely satisfied. When validating the pattern the developer may have to deal with the pattern expressed in some particular formalism. For this reason, we identify three desirable quality attributes for the underlying specification language: succinctness, ease of validation and modifiability. We show that typical formalisms such as temporal logics or automata fail at some extent to support these features. In this work we propose FVS, a graphical scenario-based language, as a possible alternative to specify behavioral properties. We illustrate FVS' features by describing one of the most commonly used pattern, the Response Pattern, and several variants of it. Other known patterns such as the Precedence pattern and the Constrained Chain pattern are also discussed. We also thoroughly compare FVS against other used approaches.

Registro:

Documento: Conferencia
Título:Specification patterns can be formal and still easy
Autor:Asteasuain, F.; Braberman, V.
Ciudad:Redwood City, CA
Filiación:FCEyN, University of Buenos Aires, Argentina
Palabras clave:Behavioral properties; Modifiability; Property Specification; Quality attributes; Response patterns; Scenario-based languages; Software verification; Specification patterns; Formal languages; Knowledge engineering; Software engineering; Specification languages; Specifications; Model checking
Año:2010
Página de inicio:430
Página de fin:436
Título revista:22nd International Conference on Software Engineering and Knowledge Engineering, SEKE 2010
Título revista abreviado:SEKE - Proc. Int. Conf. Softw. Eng. Knowl. Eng.
Registro:https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_18917062_v_n_p430_Asteasuain

Referencias:

  • Alfonso, A., Braberman, V., Kicillof, N., Olivero, A., Visual timed event scenarios (2004) Proceedings of the 26th International Conference on Software Engineering, p. 177. , IEEE Computer Society
  • Autili, M., Inverardi, P., Pelliccione, P., Graphical scenarios for specifying temporal properties: An automated approach (2007) Automated Software Engineering, 14 (3), pp. 293-340. , DOI 10.1007/s10515-007-0012-6
  • Autili, M., Pelliccione, P., Towards a Graphical Tool for Refining User to System Requirements (2008) Electronic Notes in Theoretical Computer Science, 211 (C), pp. 147-157. , DOI 10.1016/j.entcs.2008.04.037, PII S1571066108002521
  • Braberman, V., Garbervestky, D., Kicillof, N., Monteverde, D., Olivero, A., Speeding up model checking of timed-models by combining scenario specialization and live component analysis (2009) FORMATS, p. 72. , Springer
  • Braberman, V., Kicillof, N., Olivero, A., A scenario-matching approach to the description and model checking of real-time properties (2005) IEEE Transactions on Software Engineering, 31 (12), pp. 1028-1041. , DOI 10.1109/TSE.2005.131
  • Cobleigh, R., Avrunin, G., Clarke, L., User guidance for creating precise and accessible property specifications (2006) Proceedings of the 14th ACM SIGSOFT International Symposium on Foundations of Software Engineering, p. 218. , ACM
  • Dillon, L., Kutty, G., Moser, L., Melliar-Smith, P., Ramakrishna, Y., A graphical interval logic for specifying concurrent systems (1994) ACM Transactions on Software Engineering and Methodology (TOSEM), 3 (2), pp. 131-165
  • Dwyer, M., Avrunin, G., Corbett, J., Specification PatternsWeb Site, , http://patterns.projects.cis.ksu.edu/documentation/patterns.shtml
  • Dwyer, M., Avrunin, G., Corbett, J., Patterns in property specifications for finite-state verification (1999) Proceedings of the 21st International Conference on Software Engineering ICSE, 99
  • Giannakopoulou, D., Magee, J., Fluent model checking for event based systems (2003) Proceedings of the 9th European Software Engineering Conference Held Jointly with 11th ACM SIGSOFT International Symposium on Foundations of Software Engineering, p. 266. , ACM
  • Harel, D., Marelly, R., Playing with time: On the specification and execution of time-enriched lscs MASCOTS'02, pp. 193-202. , IEEE Computer Society
  • Holzmann, G., The logic of bugs (2002) ACM SIGSOFT Software Engineering Notes, 27 (6), p. 87
  • Konrad, S., Cheng, B., Real-time specification patterns (2005) Proceedings of the 27th ICSE, pp. 372-381. , ACM
  • Laroussinie, F., Markey, N., Schnoebelen, P., Temporal logic with forgettable past (2002) Proceedings-Symposium on Logic in Computer Science, pp. 383-392. , 2002
  • Markey, N., Temporal logic with past is exponentially more succinct (2003) EATCS Bull, 79, pp. 122-128
  • Paun, D., Chechik, M., Events in linear-time properties (1999) Proceedings of 4th International Conference on Requirements Engineering, , Citeseer
  • Pradella, M., Pietro, P.S., Spoletini, P., Morzenti, A., Practical model checking of LTL with past (2003) ATVA03: 1st Workshop on Automated Technology for Verification and Analysis, , Citeseer
  • Viggers, R.W.R., Viggers, K., Implementing protocols via declarative event patterns (2004) ACM Sigsoft International Symposium on FSE(FSE-12), pp. 158-169
  • Sengupta, B., Cleaveland, R., Triggered message sequence charts (2002) SIGSOFT FSE, pp. 167-176
  • Smith, M.H., Holzmann, G.J., Etessami, K., Events and constraints: A graphical editor for capturing logic requirements of programs (2001) Proceedings of the IEEE International Conference on Requirements Engineering, pp. 14-22
  • Smith, R.L., Avrunin, G.S., Clarke, L.A., Osterweil, L.J., PROPEL: An approach supporting property elucidation (2002) Proceedings - International Conference on Software Engineering, pp. 11-21
  • Uchitel, S., Kramer, J., Magee, J., Negative scenarios for implied scenario elicitation (2002) Proc. of FSE'02, pp. 109-118. , ACM PressA4 - Knowledge Systems Institute Graduate School

Citas:

---------- APA ----------
Asteasuain, F. & Braberman, V. (2010) . Specification patterns can be formal and still easy. 22nd International Conference on Software Engineering and Knowledge Engineering, SEKE 2010, 430-436.
Recuperado de https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_18917062_v_n_p430_Asteasuain [ ]
---------- CHICAGO ----------
Asteasuain, F., Braberman, V. "Specification patterns can be formal and still easy" . 22nd International Conference on Software Engineering and Knowledge Engineering, SEKE 2010 (2010) : 430-436.
Recuperado de https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_18917062_v_n_p430_Asteasuain [ ]
---------- MLA ----------
Asteasuain, F., Braberman, V. "Specification patterns can be formal and still easy" . 22nd International Conference on Software Engineering and Knowledge Engineering, SEKE 2010, 2010, pp. 430-436.
Recuperado de https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_18917062_v_n_p430_Asteasuain [ ]
---------- VANCOUVER ----------
Asteasuain, F., Braberman, V. Specification patterns can be formal and still easy. SEKE - Proc. Int. Conf. Softw. Eng. Knowl. Eng. 2010:430-436.
Available from: https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_18917062_v_n_p430_Asteasuain [ ]