Artículo
Abstract:
Multi-core processors are ubiquitous in all market segments from embedded to high performance computing, but only few applications can efficiently utilize them. Existing parallel frameworks aim to support thread-level parallelism in applications, but the imposed overhead prevents their usage for small problem instances. This work presents Micro-threads (Mth) a hardware-software proposal focused on a shared thread management model enabling the use of parallel resources in applications that have small chunks of parallel code or small problem inputs by a combination of software and hardware: delegation of the resource control to the application, an improved mechanism to store and fill processor's context, and an efficient synchronization system. Four sample applications are used to test our proposal: HSL filter (trivially parallel), FFT Radix2 (recursive algorithm), LU decomposition (barrier every cycle) and Dantzig algorithm (graph based, matrix manipulation). The results encourage the use of Mth and could smooth the use of multiple cores for applications that currently can not take advantage of the proliferation of the available parallel resources in each chip. © 2002-2011 IEEE.
Registro:
| Documento: | Artículo |
| Título: | Mth: Codesigned Hardware/Software Support for Fine Grain Threads |
| Autor: | Gonzalez Marquez, D.; Cristal, A.; Mocskos, E. |
| Filiación: | Computer Science Department, Facultad de Ciencias Exactas y Naturales, Universidad de Buenos Aires (C1428EGA), Buenos Aires, Argentina CSC-CONICET, Buenos Aires, Argentina Barcelona Supercomputing Center, Instituto de Investigacion en Inteligencia Artificial (IIIA-CSIC), Department of Computer Architecture, Universitat Politecnica de Catalunya, Barcelona, Spain |
| Palabras clave: | Multicore processing; Multithreading; Parallel architectures; Parallel programming; Application programs; Graphic methods; Hardware; Hardware-software codesign; Multitasking; Parallel architectures; Parallel processing systems; Parallel programming; Reconfigurable hardware; Ubiquitous computing; High performance computing; Multi-core processing; Multi-core processor; Multi-threading; Recursive algorithms; Software and hardwares; Synchronization systems; Thread level parallelism; Multicore programming |
| Año: | 2016 |
| Volumen: | PP |
| Número: | 99 |
| DOI: | http://dx.doi.org/10.1109/LCA.2016.2606383 |
| Título revista: | IEEE Computer Architecture Letters |
| Título revista abreviado: | IEEE Comput. Archit. Lett. |
| ISSN: | 15566056 |
| Registro: | https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_15566056_vPP_n99_p_GonzalezMarquez |
Referencias:
- Binkert, N., Beckmann, B., Black, G., Reinhardt, S.K., Saidi, A., Basu, A., Hestness, J., Wood, D.A., The gem5 simulator (2011) SIGARCH Comput. Archit. News, 39 (2), pp. 1-7. , Aug
- Blake, G., Dreslinski, R.G., Mudge, T., Flautner, K., Evolution of thread-level parallelism in desktop applications (2010) SIGARCH Comput. Archit. News, 38 (3), pp. 302-313. , Jun
- Endo, F., Courousse, D., Charles, H.-P., Micro-architectural simulation of in-order and out-of-order arm microprocessors with gem5 2014 Int. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation, July 2014, pp. 266-273
- Fillo, M., Keckler, S.W., Dally, W.J., Carter, N.P., Chang, A., Gurevich, Y., Lee, W.S., The M-Machine multicomputer (1995) Proc. of the 28th Int. Symp. on Microarch, pp. 146-156. , Nov
- Kumar, S., Hughes, C.J., Nguyen, A., Carbon: Architectural support for fine-grained parallelism on chip multiprocessors (2007) SIGARCH Comput. Archit. News, 35 (2), pp. 162-173. , Jun
- Madriles, C., López, P., Codina, J.M., Gibert, E., Latorre, F., Mar-Tinez, A., Martinez, R., Gonzalez, A., Boosting single-thread performance in multi-core systems through fine-grain multi-threading (2009) SIGARCH Comput. Archit. News, 37 (3), pp. 474-483. , Jun
- Michailidis, P., Margaritis, K., Implementing parallel LU fac-torization with pipelining on a multicore using openmp 2010 IEEE 13th Int. Conf. on Comp. Sci. and Eng., Dec 2010, pp. 253-260
- Mutlu, O., Stark, J., Wilkerson, C., Patt, Y.N., Runahead execution: An alternative to very large instruction windows for out-of-order processors (2003) Proc. of the 9th HPCA
- Price, G.W., Lowenthal, D.K., A comparative analysis of fine-grain threads packages (2003) J Parallel Distr Com, 63 (11), pp. 1050-1063. , Nov
- Sanchez, D., Yoo, R.M., Kozyrakis, C., Flexible architectural support for fine-grain scheduling (2010) Proc. of the 15th ASPLOS, pp. 311-322
- Zhong, H., Lieberman, S.A., Mahlke, S.A., Extending mul-ticore architectures to exploit hybrid parallelism in single-thread applications (2007) Proc. of the 13th HPCA, pp. 25-36
Citas:
---------- APA ----------
Gonzalez Marquez, D., Cristal, A. & Mocskos, E. (2016) . Mth: Codesigned Hardware/Software Support for Fine Grain Threads. IEEE Computer Architecture Letters, PP(99).http://dx.doi.org/10.1109/LCA.2016.2606383
---------- CHICAGO ----------
Gonzalez Marquez, D., Cristal, A., Mocskos, E. "Mth: Codesigned Hardware/Software Support for Fine Grain Threads" . IEEE Computer Architecture Letters PP, no. 99 (2016).http://dx.doi.org/10.1109/LCA.2016.2606383
---------- MLA ----------
Gonzalez Marquez, D., Cristal, A., Mocskos, E. "Mth: Codesigned Hardware/Software Support for Fine Grain Threads" . IEEE Computer Architecture Letters, vol. PP, no. 99, 2016.http://dx.doi.org/10.1109/LCA.2016.2606383
---------- VANCOUVER ----------
Gonzalez Marquez, D., Cristal, A., Mocskos, E. Mth: Codesigned Hardware/Software Support for Fine Grain Threads. IEEE Comput. Archit. Lett. 2016;PP(99).http://dx.doi.org/10.1109/LCA.2016.2606383
