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Abstract:

The introduction of high-performance applications such as multimedia applications into SoCs led the manufacturers to provide embedded SoCs able to offer an important computing power which makes it possible to answer the increasing requirements of future evolutions of these applications. One of the adopted solutions is the use of multiprocessor SoCs. In this paper, we present a joint SW/HW design exploration methodology for multiprocessor SoCs. The system model relies on transaction-level component-based models for modeling parallel software and multiprocessor hardware. Our proposal comprises two original points. First, we propose a composable software-level scheduler constraints synthesis technique. Second, we present a combined software-level and exploratory hardwarelevel schedulers. The methodology has the advantage of combining real-time requirements of software with effective exploitation of multiprocessor hardware. We describe and apply the methodology to synthesize a scheduler of a slice-based MPEG-4 video encoder on the multiprocessor Cake SoCs. © Springer Science+Business Media, LLC 2010.

Registro:

Documento: Artículo
Título:A scheduler synthesis methodology for joint SW/HW design exploration of SoC
Autor:Assayad, I.; Yovine, S.
Filiación:ENSEM, University of Hassan II Ain Chock, Oasis Casablanca, Morocco
Departamento de Computacion, Universidad de Buenos Aires, Researcher at CONICET, Buenos Aires, Argentina
Palabras clave:Exploration; Multiprocessor system-on-chips (SoCs); Real-time requirements; Scheduling; SW/HW design; Component-based models; Computing power; Exploration; High performance applications; MPEG-4 video encoders; Multi-processor hardware; Multimedia applications; Multiprocessor system on chips; Parallel software; Real time requirement; SW/HW design; Synthesis methodology; Synthesis techniques; System models; Design; Motion Picture Experts Group standards; Scheduling; Timing jitter; Multiprocessing systems
Año:2010
Volumen:14
Número:2
Página de inicio:75
Página de fin:103
DOI: http://dx.doi.org/10.1007/s10617-010-9051-5
Título revista:Design Automation for Embedded Systems
Título revista abreviado:Des Autom Embedded Syst
ISSN:09295585
CODEN:DAESF
Registro:https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_09295585_v14_n2_p75_Assayad

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Citas:

---------- APA ----------
Assayad, I. & Yovine, S. (2010) . A scheduler synthesis methodology for joint SW/HW design exploration of SoC. Design Automation for Embedded Systems, 14(2), 75-103.
http://dx.doi.org/10.1007/s10617-010-9051-5
---------- CHICAGO ----------
Assayad, I., Yovine, S. "A scheduler synthesis methodology for joint SW/HW design exploration of SoC" . Design Automation for Embedded Systems 14, no. 2 (2010) : 75-103.
http://dx.doi.org/10.1007/s10617-010-9051-5
---------- MLA ----------
Assayad, I., Yovine, S. "A scheduler synthesis methodology for joint SW/HW design exploration of SoC" . Design Automation for Embedded Systems, vol. 14, no. 2, 2010, pp. 75-103.
http://dx.doi.org/10.1007/s10617-010-9051-5
---------- VANCOUVER ----------
Assayad, I., Yovine, S. A scheduler synthesis methodology for joint SW/HW design exploration of SoC. Des Autom Embedded Syst. 2010;14(2):75-103.
http://dx.doi.org/10.1007/s10617-010-9051-5