Artículo
Abstract:
Instruction Scheduling is the task of deciding what instruction will be executed at which unit of time. The objective is to extract maximum instruction level parallelism for the code. Compilers designed for VLIW and EPIC architectures do static instruction scheduling in a back-end pass. This pass, known as scheduler, needs to have full knowledge of the execution time of each instruction. But memory access instructions have a variable latency, depending on their locality and the memory hierarchy architecture. The scheduler must assume a constant value, usually the execution time assigned to a hit. At execution a miss may reduce the parallelism because idle cycles may appear before the instructions that need the data. This paper describes a statistic model to evaluate how sensitive are the scheduling algorithms to the variable time operations. We present experimental measures taken over two static scheduling algorithms based on software pipelining. © Springer-Verlag Berlin Heidelberg 1999.
Registro:
| Documento: | Artículo |
| Título: | Influence of variable time operations in static instruction scheduling |
| Autor: | Borensztejn, P.; Barrado, C.; Labarta, J. |
| Ciudad: | Toulouse |
| Filiación: | Dep. de Computación, UBA, Argentina Dep. de Arquitectura de Computadores, UPC, Spain |
| Palabras clave: | Constant values; EPIC architecture; Execution time; Instruction level parallelism; Instruction scheduling; Memory hierarchy; Software pipelining; Variable latencies; Scheduling; Very long instruction word architecture |
| Año: | 1999 |
| Volumen: | 1685 LNCS |
| Página de inicio: | 213 |
| Página de fin: | 216 |
| Título revista: | 5th International Conference on Parallel Processing, Euro-Par 1999 |
| Título revista abreviado: | Lect. Notes Comput. Sci. |
| ISSN: | 03029743 |
| Registro: | https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_03029743_v1685LNCS_n_p213_Borensztejn |
Referencias:
- Barrado, C., Labarta, J., Hamiltonian recurrence for ILP (1997) EuroPar
- Borensztejn, P., Barrado, C., Labarta, J., The scheduling graph in the variable time model Report UPC-DAC-1999-18
- Lam, M., Software pipelining: An effective scheduling technique for VLIW machines (1988) Proceedings SIGPLAN'88 PLDI, pp. 318-328
- Llosa, J., Valero, M., Ayguadé, E., González, A., Hypernode reduction modulo scheduling (1995) Micro-28, pp. 350-360. , Dec
- Rau, B., Iterative modulo scheduling: An algorithm for software pipelining loops (1994) IEEE Micro-27, pp. 63-74. , NovA4 - Association of Computer Machinery; International Federation of Information Processing
Citas:
---------- APA ----------
Borensztejn, P., Barrado, C. & Labarta, J. (1999) . Influence of variable time operations in static instruction scheduling. 5th International Conference on Parallel Processing, Euro-Par 1999, 1685 LNCS, 213-216.Recuperado de https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_03029743_v1685LNCS_n_p213_Borensztejn [ ]
---------- CHICAGO ----------
Borensztejn, P., Barrado, C., Labarta, J. "Influence of variable time operations in static instruction scheduling" . 5th International Conference on Parallel Processing, Euro-Par 1999 1685 LNCS (1999) : 213-216.Recuperado de https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_03029743_v1685LNCS_n_p213_Borensztejn [ ]
---------- MLA ----------
Borensztejn, P., Barrado, C., Labarta, J. "Influence of variable time operations in static instruction scheduling" . 5th International Conference on Parallel Processing, Euro-Par 1999, vol. 1685 LNCS, 1999, pp. 213-216.Recuperado de https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_03029743_v1685LNCS_n_p213_Borensztejn [ ]
---------- VANCOUVER ----------
Borensztejn, P., Barrado, C., Labarta, J. Influence of variable time operations in static instruction scheduling. Lect. Notes Comput. Sci. 1999;1685 LNCS:213-216.Available from: https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_03029743_v1685LNCS_n_p213_Borensztejn [ ]
